1. Field of the Invention
The present invention relates to a semiconductor substrate, a process for production thereof, and a semiconductor device; particularly to a semiconductor substrate suitably used in formation of a vertical power semiconductor device, and a process for production of the semiconductor substrate.
2. Description of the Related Art
Power semiconductor devices such as IGBT (insulated-gate bipolar transistor), thyristor and the like have a pnpn four-layer structure and are superior in on-resistance characteristic; therefore, they are in use in the fields requiring a relatively high breakdown voltage or a large electric current. An example of power semiconductor devices is a vertical IGBT which comprises a p.sup.+ type single-crystal silicon substrate (this becomes a collector), an n.sup.- type base layer formed thereon, a p.sup.- type base layer formed thereon, an emitter (a n.sup.+ type diffusion layer) formed thereon, and a gate electrode formed thereon via an insulating film. The n.sup.- type base layer of this vertical IGBT is formed in a fairly large thickness so as to have a high breakdown voltage and has a high resistance.
Processes for producing a substrate for vertical IGBT includes a process which comprises forming an n.sup.- type single-crystal silicon epitaxial layer on a p.sup.+ type single-crystal silicon substrate. This process, however, has a limitation in achieving a high resistance and a large thickness.
For production of a substrate capable of achieving a high breakdown voltage, a process of directly bonding two substrates is disclosed in Toshiba Review, Vol. 41, No. 12, pp. 1000-1003 (1986). FIGS. 5(a) to 5(d) are sectional views showing the steps employed in producing a substrate according to the above process of direct bonding. First, phosphorus ion is implanted into a n.sup.- type single-crystal silicon substrate (1) to form an n.sup.+ type buffer layer (21) FIGS. 5(a) and 5(b)!. Into the n.sup.+ type buffer layer is implanted boron ion to form a thin p.sup.+ diffusion layer (22) FIG. 5(c)!. Then, on the p.sup.+ type diffusion layer side of the n.sup.- type silicon substrate is bonded to a p.sup.+ type single-crystal silicon substrate (3), and the bonded wafer is heat-treated. Thus, a n.sup.- /n.sup.+ /p.sup.+ three-layer substrate is completed FIG. 5(d)!. In this way, a high-resistance layer is formed on a low-resistance substrate.
In the above process, the n.sup.+ type buffer layer (21) is formed in order to suppress the minority carrier (holes in this case) which is implanted from the p.sup.+ type single-crystal silicon substrate (3) into the n.sup.- type single-crystal silicon substrate (1) (n.sup.- type base layer) when the device obtained using the three-layer substrate is in an on-state. As the total amount of impurity in the n.sup.+ type buffer layer is larger, the recombination probability of carrier is higher, serving to shorten the turn-off time of device.
In the n.sup.- /n.sup.+ /p.sup.+ three-layer substrate produced by, for example, the above process of direct bonding of two single-crystal silicon substrates, since the amount of the holes implanted into the n.sup.- type base layer is determined only by the total amount of impurity in the n.sup.+ type buffer layer, the shortening of turn-off time of device has had a limitation. Also, in bonding of two single-crystal silicon substrates, there have been problems of small bonding strength and easy generation of voids at the interface of the two substrates.